From US patent application No. 2007086232 it is known to connect circuits from a row of a static memory matrix in a ring oscillator configuration. By measuring the oscillation frequency of such a ring oscillator timing properties of the memory cells can be tested. In fact, the ring-oscillator represents a delay circuit, with a delay that is representative of the properties of the memory cells. The delay is measured from the oscillation frequency.
Conventionally, columns in a memory matrix are associated with bit lines (conductors) extending along the columns, for accessing data from selected cells in the column, and rows in the memory matrix are associated with word lines (conductors) to control connection of cells to bit-lines on a row by row basis. The memory cells have cross-coupled inverters and access transistors coupling the cross-coupled inverters to bit-lines.
US patent application 2007086232 shows various embodiments of the ring oscillator. In each of these embodiments circuits from different cells in a row of the matrix are interconnected. In one embodiment, additional conductors are provided to couple the inputs of the inverters of each cell in the row to the bit-lines of the cell in a previous column. The input of each inverter is also coupled to the gate of the access transistor that couples the output of the inverter to the bit line. Thus, a ring-oscillator is formed, wherein the cross-coupled inverters of a row are coupled in series in a circuit loop. In another embodiment the cross-coupling between the inverters is broken-up. In this embodiment the inverters in each cell of a row are coupled in series and additional conductors are provided between the inputs and outputs of series arrangements of inverters of the different cells in the row, bypassing the bit-lines. In this embodiment the access transistors are used as loads of the inverters, with channels coupled between the outputs of the inverters and the bit-lines. The gates of the access transistors are grounded. Thus, a ring-oscillator is formed, wherein the series arrangements inverters of the rows are coupled in series in a circuit loop.
For circuit design purposes it is desirable that the layout of the cells that make up part the ring-oscillator fit within shape and size of the regular static memory cells of the matrix. In the embodiments of US patent application 2007086232 it is difficult to fit the ring-oscillator into a row of the same row height as rows of normal memory cells. In the first embodiment, a complete static memory cells used except for word lines, and conductors between bit lines and inverters are added, as well as conductors between inverter inputs and gates of access transistors, plus contacts between these conductors and various components. Also in the second embodiment extra room is needed for additional conductors between the channels of the transistors in the inverters in adjacent cells.
In addition the embodiment with the cross-coupled inverters can be disadvantageous because the cross-coupled inventors counteract each other's transitions, which makes the oscillation frequency of the ring oscillator strongly dependent on the ratio of the output transistors of the inverters. As a result oscillation frequency may have limited usefulness for testing the memory cells.